A random testing method for testing processors by randomly generating test instruction sequences and test data on the basis of random numbers has been known as a processor-operation verification method. There is also a method for testing processor operations by comparing a result value obtained by causing a processor to execute random testing with an expectation value obtained by causing a simulator to simulate the operation of the processor. The simulator is, for example, a simulation program realized by software. The simulator performs simulation testing for logic specifications of the processor.
Examples of related art include Japanese Laid-open Patent Publication No. 04-247534, Japanese Laid-open Patent Publication No. 08-166892, and Japanese Laid-open Patent Publication No. 11-338727.
Operations defined based on the logic specifications of the processor are incorporated into the processor. Thus, it has been though that, even for processors of various models whose model numbers and revision numbers are different, simulation may be able to be executed using the same simulator if the logic specifications are the same. However, actual simulation revealed that there are cases in which not only a logic failure or a processor device failure but also a model-dependent operation in the logic specifications causes a mismatch between the result value and the expectation value. That is, when predetermined test instruction sequences are executed, model-dependent operations that may not be anticipated by an examiner may occur and it has become clear that there is a possibility in that processors of different models even with the same logic specifications perform execution operations of different test instruction sequences.
However, the examiner may not know whether or not the processor to be tested has a model-dependent operation in the logic specifications. Thus, when an actual simulation indicates a mismatch between the result value and the expectation value, it is desirable to analyze whether or not it is caused by a model-dependent operation. Thus, based on a result of the analysis, the simulator is revised or the test conditions are changed to execute simulation again.
Such analysis of the cause of the mismatch between the result value and the expectation value, revision of the simulator, and so on involve complex processes, which lead to increases in the time and man-hours for the testing. Accordingly, the processor operation may not be efficiently verified. In addition, even when re-simulation is further performed through revision of the simulator or the like, there are cases in which a failure or defect originating in the processor may not be detected. That is, the accuracy of the operation verification declines.